USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
Table 9.8 SPI Timing Values (60 MHz Operation)
SYMBOL
t
fc
t
ceh
t
clq
t
dh
t
os
t
oh
t
ov
t
cel
t
ceh
Clock frequency
Chip enable (SPI_CE_EN) high time
Clock to input data
Input data hold time
Output setup time
Output hold time
Clock to output valid
Chip enable (SPI_CE_EN) low to first clock
Last clock to chip enable (SPI_CE_EN) high
0
5
5
4
12
12
50
9
DESCRIPTION
MIN
TYP
MAX
60
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
9.6
Clock Specifications
The device can accept a 24 MHz single-ended clock oscillator input. REFCLK should be driven with a
clock that adheres to the specifications outlined in
9.6.1
External Reference Clock (REFCLK)
The following input clock specifications are suggested:
50% duty cycle
±
10%
±
350 PPM
The input frequency of REFCLK is user configurable. Refer to
for
additional information on configuring a reference clock input.
Note:
The external clock is recommended to conform to the signalling levels designated in the
JEDEC specification on 1.2V CMOS Logic.
SMSC USB3813
65
Revision 1.0 (06-17-13)
DATASHEET
SMSC [ SMSC CORPORATION ]
