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S25FL032A0LMFI001 参数 Datasheet PDF下载

S25FL032A0LMFI001图片预览
型号: S25FL032A0LMFI001
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位CMOS 3.0伏闪存与50MHz的SPI (串行外设接口)总线 [32 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus]
分类和应用: 闪存
文件页数/大小: 36 页 / 944 K
品牌: SPANSION [ SPANSION ]
 浏览型号S25FL032A0LMFI001的Datasheet PDF文件第24页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第25页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第26页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第27页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第29页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第30页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第31页浏览型号S25FL032A0LMFI001的Datasheet PDF文件第32页  
D a t a S h e e t ( P r e l i m i n a r y )  
9.12.1  
Release from Deep Power Down and Read Electronic Signature (RES)  
The device features an 8-bit Electronic Signature, which can be read using the RES command. See  
Figure 9.13 and Table 9.4 for the command sequence and signature value. The Electronic Signature is not to  
be confused with the identification data obtained using the RDID command. The device offers the Electronic  
Signature so that it can be used with previous devices that offered it; however, the Electronic Signature  
should not be used for new designs, which should read the RDID data instead.  
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each  
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is  
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the  
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to  
output the Electronic Signature repeatedly.  
When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of tRES, as  
previously described. The RES command always provides access to the Electronic Signature of the device  
and can be applied even if DP mode has not been entered.  
Any RES command issued while an erase, program, or WRSR operation is in progress not executed, and the  
operation continues uninterrupted.  
Figure 9.13 Release from Deep Power Down and  
Read Electronic Signature (RES) Command Sequence  
CS#  
2
28 29 30  
31 32 33 34  
1
8
36 37  
9
35  
38  
0
3
4
5
6
7
10  
SCK  
t
RES  
3 Dummy Bytes  
Command  
SI  
3
1
0
2
23 22  
MSB  
21  
Hi-Z  
7
6
5
4
3
2
1
SO  
0
MSB  
Electronic ID out  
Standby Mode  
Deep Power-down Mode  
Table 9.4 Command Definitions  
One-Byte  
Address  
Bytes  
Dummy  
Byte  
Operation  
Command  
READ  
FAST_READ  
RDID  
Description  
Command Code  
03H (0000 0011)  
0BH (0000 1011)  
9FH (1001 1111)  
06H (0000 0110)  
04H (0000 0100)  
D8H (1101 1000)  
C7H (1100 0111)  
02H (0000 0010)  
05H (0000 0101)  
01H (0000 0001)  
B9H (1011 1001)  
ABH (1010 1011)  
Data Bytes  
Read Data Bytes  
3
3
0
0
0
3
0
3
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1 to  
Read  
Read Data Bytes at Higher Speed  
Read Identification (Note 1)  
Write Enable  
1 to ∞  
1 to 3  
WREN  
WRDI  
SE  
0
Write Control  
Write Disable  
0
Sector Erase  
0
Erase  
Program  
BE  
Bulk (Chip) Erase  
0
PP  
Page Program  
1 to 256  
RDSR  
WRSR  
DP  
Read from Status Register  
Write to Status Register  
Deep Power Down  
1 to ∞  
Status Register  
1
0
0
Release from Deep Power Down  
Power Saving  
RES  
Release from Deep Power Down and  
Read Electronic Signature (Note 2)  
ABH (1010 1011)  
0
3
1 to ∞  
Notes  
1. The S25FL032A has a manufacturer ID of 01h, and a device ID consisting of the memory type (02h) and the memory capacity (15h).  
2. The S25FL032A has an Electronic Signature ID of 15h.  
26  
S25FL032A  
S25FL032A_00_C0 September 1, 2006