D at a
S hee t
(Adva nce
In for m ation)
Figure 11.7
Reset Timings
RY/BY#
CE#, OE#
t
RH
RESET#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Table 11.5
Power-up Sequence Timings
Parameter
t
VCS
t
VIOS
t
RH
Notes
1. V
IO
< V
CC
+ 200 mV.
2. V
IO
and V
CC
ramp must be synchornized during power up.
3. If RESET# is not stable for t
VCS
or t
VIOS
:
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4. V
CC
maximum power-up current (RST=V
IL
) is 20 mA.
Description
Reset Low Time from rising edge of V
CC
(or last Reset pulse) to
rising edge of RESET#
Reset Low Time from rising edge of V
IO
(or last Reset pulse) to
rising edge of RESET#
Reset High Time before Read
Min
Min
Max
Speed
35
35
200
Unit
µs
µs
ns
November 21, 2006 S29GL-P_00_A3
S29GL-P MirrorBit
TM
Flash Family
53
SPANSION [ SPANSION ]
