D at a
S hee t
(Adva nce
In for m ation)
Figure 11.9
Program Operation Timings
Program Command
Sequence
(last two cycles)
t
WC
Addresses
555h
t
AS
PA
t
AH
CE#
OE#
t
WP
WE#
t
CS
t
DS
Data
t
DH
PD
t
BUSY
RY/BY#
t
WPH
Read
Status
Data (last two cycles)
PA
PA
t
CH
t
WHWH1
A0h
Status
D
OUT
t
RB
V
CC
t
VCS
Notes
1. PA = program address, PD = program data, D
OUT
is the true data at the program address.
2. Illustration shows device in word mode.
Figure 11.10
Accelerated Program Timing Diagram
V
HH
ACC
V
IL
or V
IH
t
VHH
t
VHH
V
IL
or V
IH
Notes
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See
and
for test specifications.
November 21, 2006 S29GL-P_00_A3
S29GL-P MirrorBit
TM
Flash Family
55