Data
Sheet
(Advan ce
Infor m a tio n)
Figure 11.11
Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
t
WC
Addresses
2AAh
t
AS
SA
555h for chip erase
Read Status Data
VA
t
AH
VA
CE#
OE#
t
WP
WE#
t
CS
t
DS
t
CH
t
WPH
t
WHWH2
t
DH
Data
55h
30h
10 for Chip Erase
In
Progress
Complete
t
BUSY
RY/BY#
t
VCS
V
CC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status.”
2. These waveforms are for the word mode
t
RB
Figure 11.12
Data# Polling Timings (During Embedded Algorithms)
t
RC
Addresses
VA
t
ACC
t
CE
CE#
t
CH
OE#
t
OEH
WE#
t
OH
DQ7
High Z
VA
VA
t
OE
t
DF
Complement
Complement
True
Valid Data
High Z
DQ6–DQ0
t
BUSY
RY/BY#
Status Data
Status Data
True
Valid Data
Notes
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
2. t
OE
for data polling is 45 ns when V
IO
= 1.65 to 2.7 V and is 35 ns when V
IO
= 2.7 to 3.6 V
56
S29GL-P MirrorBit
TM
Flash Family
S29GL-P_00_A3 November 21, 2006
SPANSION [ SPANSION ]
