D at a
S hee t
(Adva nce
In for m ation)
12. Appendix
This section contains information relating to software control or interfacing with the Flash device. For
additional information and assistance regarding software, see
www.spansion.com.
12.1
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Tables
define the valid register command sequences.
Writing incorrect address and
data values or writing them in the improper sequence can place the device in an unknown state.
A reset
command is then required to return the device to reading array data.
Table 12.1
S29GL-P Memory Array Command Definitions, x16
Cycles
Bus Cycles (Notes
1–5)
First
Addr
RA
XXX
555
555
555
555
55
555
555
SA
555
555
XXX
XXX
XXX
XXX
555
555
XXX
XXX
555
555
Data
RD
F0
AA
AA
AA
AA
98
AA
AA
29
AA
AA
A0
80
80
90
AA
AA
B0
30
AA
AA
2AA
2AA
55
55
555
555
88
90
XX
00
2AA
2AA
PA
SA
XXX
XXX
2AA
2AA
55
55
PD
30
10
00
55
55
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
555
555
F0
20
2AA
2AA
55
55
555
SA
A0
25
PA
SA
PD
WC
WBL
PD
WBL
PD
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
555
90
90
90
90
X00
X01
[SA]X02
X03
01
227E
X0E
X0F
Second
Addr
Data
Third
Addr
Data
Fourth
Addr
Data
Fifth
Addr
Data
Sixth
Addr
Data
Command (Notes)
Read
Reset
Autoselect (8,9)
Manufacturer ID
Device ID
Sector Protect Verify
Secure Device Verify
1
1
4
4
4
4
1
4
3
1
3
3
2
2
2
2
6
6
1
1
3
4
CFI Query
Program
Write to Buffer
Program Buffer to Flash (Confirm)
Write-to-Buffer-Abort Reset
Unlock Bypass
Enter
Program
Sector Erase
Chip Erase
Reset
Chip Erase
Sector Erase
Erase Suspend/Program Suspend
Erase Resume/Program Resume
Secured Silicon Sector Entry
Secured Silicon Sector Exit
Legend
X = Don’t care
RA = Address of the memory to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A
max
–A16 uniquely select any sector.
WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
Notes
1. See
for description of bus operations.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits A
MAX
:A16 are don’t cares for unlock and command cycles, unless SA or PA required. (A
MAX
is the Highest Address pin.).
6. No unlock or command cycles required when reading array data.
November 21, 2006 S29GL-P_00_A3
S29GL-P MirrorBit
TM
Flash Family
61
SPANSION [ SPANSION ]
