CY28324
Pin Definitions
Pin Name
X1
Pin No.
3
Pin
Type
I
Pin Description
Crystal Connection or External Reference Frequency Input:
This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
Crystal Connection:
Connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Reference Clock 0/Current Multiplier Selection 0:
3.3V 14.318-MHz clock
output. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as
follows:
MULTSEL1:0
00 = I
OH
is 4 x IREF
01 = I
OH
is 5 x IREF
10 = I
OH
is 6 x IREF
11 = I
OH
is 7 x IREF
X2
REF0/MULTSEL0
4
48
O
I/O
REF1/MULTSEL1
1
I/O
Reference Clock 1/Current Multiplier Selection 1:
3.3V 14.318-MHz clock
output. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as
follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = I
OH
is 5 x IREF
10 = I
OH
is 6 x IREF
11 = I
OH
is 7 x IREF
CPU Clock Outputs:
Frequency is set by the FS0:4 inputs or through the serial
input interface.
Memory Reference Clock/CPU Output Control:
The function of this pin is
controlled by the Mode input pin. When Mode input is sampled HIGH during
power-on reset, this pin will be configured as 3VMREF output. When Mode input
is sampled LOW during power-on reset, this pin will be configured as
CPU_STP# input.
3VMREF is a 3.3V output running at half the frequency of the CPU output clock.
CPU_STP# is a 3.3V LVTTL compatible input that disables CPU0, CPU0#,
CPU1 and CPU1# outputs.
Memory Reference Clock/PCI Output Control:
The function of this pin is
controlled by the Mode input pin. When Mode input is sampled HIGH during
power-on reset, this pin will be configured as 3VMREF# output. When Mode
input is sampled LOW during power-on reset, this pin will be configured as
PCI_STP# input.
3VMREF# is a 3.3V output running at half the frequency of the CPU output
clock. 3VMREF# is 180 degree out of phase with respect to 3VMREF.
PCI_STP# is a 3.3V LVTTL-compatible input that disables PCI0:6 outputs.
66-MHz Clock Outputs:
3.3V fixed 66-MHz clock.
Free-running PCI Output 0/Frequency Select 2:
3.3V free-running PCI
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in the Frequency Selection Table.
Free-running PCI Output 1/Frequency Select 3:
3.3V free-running PCI
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in the Frequency Selection Table.
Free-running PCI Output 2/Mode Selection:
3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine the functions of
3VMREF/CPU_STP# and 3VMREF#/PCI_STP#.
When Mode input is sampled HIGH during power-on reset,
3VMREF/CPU_STP# and 3VMREF#/PCI_STP# will be configured as 3VMREF
and 3VMREF# output, respectively.
When Mode input is sampled LOW during power-on reset,
3VMREF/CPU_STP# and 3VMREF#/PCI_STP# will be configured as
CPU_STP# and PCI_STP# input, respectively.
CPU0:1, CPU0:1#
3VMREF/CPU_STP
#
41, 38, 40, 37
45
O
I/O
3VMREF#/PCI_STP
#
44
I/O
3V66_0:3
PCI_F0/FS2
31, 30, 28, 27
6
O
I/O
PCI_F1/FS3
7
I/O
PCI_F2/Mode
8
I/O
Rev 1.0, November 20, 2006
Page 2 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
