CY28324
Pin Definitions
(continued)
Pin Name
PCI0/FS4
Pin No.
10
Pin
Type
I/O
Pin Description
PCI Output 0/Frequency Select 4:
3.3V PCI output. This pin also serves as
a power-on strap option to determine device operating frequency as described
in the Frequency Selection Table.
PCI Clock Output 1 to 6:
3.3V PCI clock outputs.
48MHz Output/Frequency Select 0:
3.3V fixed 48-MHz, non-spread
spectrum output. This pin also serves as a power-on strap option to determine
device operating frequency as described in
Table 4.
This output will be used as the reference clock for USB host controller in Intel
845 (Brookdale) platforms. For Intel Brookdale - G platforms, this output will
be used as the VCH reference clock.
24- or 48-MHz Output/Frequency Select 1:
3.3V fixed 24-MHz or 48-MHz
non-spread spectrum output. This pin also serves as a power-on strap option
to determine device operating frequency as described in
Table 4.
This output will be used as the reference clock for SIO devices in Intel 845
(Brookdale) platforms. For Intel Brookdale - G platforms, this output will be
used as the reference clock for both USB host controller and SIO devices. We
recommend system designer to configure this output as 48 MHz and “HIGH
Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively.
Power Down Control:
3.3V LVTTL-compatible input that places the device in
power down mode when held LOW.
SMBus Clock Input:
Clock pin for serial interface.
SMBus Data Input:
Data pin for serial interface.
System Reset Output:
Open-drain system reset output.
PCI1:6
48MHz/FS0
11, 12, 14, 15,
16, 17
22
O
I/O
24_48MHz/FS1
23
I/O
PWR_DWN#
SCLK
SDATA
RST#
42
26
25
20
I
I
I/O
O
(open-
drain)
I
I
IREF
VTT_PWRGD#
35
19
Current Reference for CPU Output:
A precision resistor is attached to this
pin, which is connected to the internal current reference.
Powergood from Voltage Regulator Module (VRM):
3.3V LVTTL input.
VTT_PWRGD# is a level sensitive strobe used to determine when FS0:4,
MODE and MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW).
Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
3.3V Power Connection:
Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output
buffers. Connect to 3.3V.
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
VDD_MREF
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_MREF,
GND_REF,
VDD_CORE
GND_CORE
2, 9, 18, 24,
32, 39, 46
P
5, 13, 21, 29,
36, 43, 47
G
Ground Connection:
Connect all ground pins to the common system ground
plane.
34
33
P
G
3.3V Analog Power Connection:
Power supply for core logic, PLL circuitry.
Connect to 3.3V.
Analog Ground Connection:
Ground for core logic, PLL circuitry.
Rev 1.0, November 20, 2006
Page 3 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
