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CY28324 参数 Datasheet PDF下载

CY28324图片预览
型号: CY28324
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的Intel㈢ Pentium㈢ 4的CPU和芯片组 [FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets]
分类和应用:
文件页数/大小: 21 页 / 208 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28324
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Data Byte Configuration Map
Data Byte 0
Bit
Bit 7
Bit 6
Bit 5
Pin#
--
--
--
Name
Spread Select2
Spread Select1
Spread Select0
‘000’ = OFF
‘001’ = Reserved
‘010’ = Reserved
‘011’ = Reserved
‘100’ = ± 0.25%
‘101’ = – 0.5%
‘110’ = ±0.5%
‘111’ = ±0.38%
SW Frequency selection bits. See
Table 4.
Description
Power-On
Default
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Byte 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
--
--
--
--
--
SEL4
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
Pin#
38, 37
41, 40
22
23
27
28
30
31
Name
CPU1, CPU1#
CPU0, CPU0#
48MHz
24_48MHz
3V66_3
3V66_2
3V66_1
3V66_0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Description
Power-On
Default
1
1
1
1
1
1
1
1
Rev 1.0, November 20, 2006
Page 6 of 21