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CY28347ZCT 参数 Datasheet PDF下载

CY28347ZCT图片预览
型号: CY28347ZCT
PDF下载: 下载PDF文件 查看货源
内容描述: 通用单芯片时钟解决方案VIA P4M266 / KM266 DDR系统 [Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 21 页 / 231 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28347
Pin Description
(continued)
[2]
Pin
6
Name
MODE/AGP0
PWR
I/O
Description
VDDAGP I/O
Power-on Bidirectional Input/Output.
At power-up, MODE is an input and
PU becomes AGP0 output after the power supply voltage crosses the input threshold
voltage. Must have 10K resistor to V
SS
. See
Table 2.
VDDAGP
I
If pin 6 is pulled down at power on reset, then this pin becomes PCI_STP#.
PU When PCI_STP# is asserted LOW, then all of the PCI signals, except the PCI_F,
stops at the next HIGH to LOW transition or stays LOW if it already is LOW.
I
Current reference programming input for CPU buffers.
A precise resistor is
attached to this pin, which is connected to the internal current reference.
8
PCI_STP#
25
28
IREF
SDATA
I/O
Serial Data Input.
Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain output
when acknowledging or transmitting data.
I
Serial Clock Input.
Conforms to the SMBus specification.
I
When PD# is asserted LOW,
the device enters power down mode. See power
PU management function.
I
O
2.5V CMOS type input to the DDR differential buffers.
This is the single-ended, SDRAM buffered output of the signal applied at
BUF_IN.
It is in phase with the DDRT(0:5) signals.
3.3V power supply for AGP clocks.
3.3V power supply for CPU (T: C) clocks.
3.3V power supply for PCI clocks.
3.3V power supply for REF clock.
2.5V power supply for CPUCS_T/C clocks.
3.3V power supply for 48M.
3.3V Common power supply.
2.5V power supply for DDR clocks.
Ground for AGP clocks.
Ground for PCI clocks.
Ground for CPU (T:C) clocks.
Ground for DDR clocks.
Ground for 48M clock.
Ground for CPUCS_T/C clocks.
Common ground.
27
26
45
46
5
51
16
55
50
22
23
34,40
9
13
54
33,39
19
47
24
SCLK
PD#
BUF_IN
FBOUT
VDDAGP
VDDC
VDDPCI
VDDR
VDDI
VDD48M
VDD
VDDD
VSSAGP
VSSPCI
VSSC
VSSD
VSS48M
VSSI
VSS
Table 2. MODE Pin-Power Management Input Control
MODE, Pin 6
(Latched Input)
0
Invalid
Pin 26
PD#
Reserved
Board Target
Trace/Term Z
50 Ohm
50 Ohm
CPU_STP#
Reserved
Reference R,
IREF = VDD/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Pin 18
PCI_STP#
Reserved
Pin 8
Table 3. Swing Select Functions Through Hardware
MULTSEL
0
1
Output Current
IOH = 4* Iref
IOH = 6* Iref
VOH@Z
1.0V@50
0.7V@50
Rev 1.0, November 20, 2006
Page 3 of 21