CY28437
Pin Description
Pin No.
1,7
2,6
4
5
8
Name
VDD_PCI
VSS_PCI
FS_E/PCI4
PCI
DF_EN/PCIF0
Type
PWR
GND
3.3V power supply for outputs.
Ground for outputs.
Description
I/O, SE,
3.3V-tolerant input for CPU frequency selection/33-MHz clock.
PU
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, SE
33 MHz clocks.
I/O, SE
3.3V LVTTL input to Enable DF pin/33-MHz Output.
PD 1 = Enable, 0 = Disable.
Intel Type-5 output buffer
9
10
SRESET_EN/PCIF I/O, PD,
3.3V LVTTL input to enable Watchdog/33-MHz clocks.
1
SE
1 = Enable, 0 = Disable
VTT_PWRGD#/PD
I, PD
3.3V LVTTL input.
This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, and FSE inputs. After VTT_PWRGD# (active LOW) assertion, this pin
becomes a real-time input for asserting power-down (active HIGH).
3.3V power supply for outputs.
11
12
13
14,15
16
VDD_48
FS_A/USB48_0
VSS_48
DOT96T, DOT96C
FS_B/USB48_1
PWR
I/O, PD,
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
GND
Ground for outputs.
O, DIF
Fixed 96-MHz clock output.
I/O, PU,
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, DIF
Differential serial reference clocks.
Outputs have overclocking capability.
17,18,19,20, SRCT/C
22,23,24,25,
31,30,33,32,
35,36
21,28,34
26,27
29
37
38
39
42
45
46
47
48
49
50
51
52
53
VDD_SRC
SRC4_SATAT,
SRC4_SATAC
VSS_SRC
VDDA
VSSA
IREF
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
FS_D/REF0
FS_C/REF1
PWR
3.3V power supply for outputs.
O, DIF
Differential serial reference clock.
Recommended output for SATA.
GND
PWR
GND
I
PWR
GND
I
I/O
PWR
I
GND
Ground for outputs.
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin,
which is connected to the internal
current reference.
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
3.3V power supply for outputs.
14.318 MHz crystal input.
Ground for outputs.
44,43,41,40 CPUT/C
O, DIF
Differential CPU clock outputs.
O, SE
14.318 MHz crystal output.
I/O, SE,
3.3V-tolerant input for CPU frequency selection/Reference clock.
PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
I/O, SE,
3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Selects test mode if pulled to V
IHFS_C
when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifications.
O
PU
33 MHz clocks/3.3V LVTTL output for Watchdog reset.
When configured as SRESET# output this output becomes open drain type with a
high (>100k ) internal pull-up resistor.
54
PCI0/SRESET#
3,55,56
DF/PCI
I/O, SE
3.3V LVTTL input for Dynamic Frequency/33-MHz clocks output.
Rev 1.0, November 20, 2006
Page 2 of 22
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