CY28437
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C, FS_D, and
FS_E input values. For all logic levels of FS_A, FS_B, FS_C,
FS_D, and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid LOW on VTT_PWRGD# has
been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,
FS_D, and FS_E transitions will be ignored, except in test
mode.
FS_C is a three-level input, when sampled at a voltage greater
than 2.1V by VTTPWRGD#, the device will enter test mode as
selected by the voltage level on the FS_B input.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Input Conditions
FS_D
FS_C
FS_B
FS_A
Output Frequency
CPU
SRC
SRC M
CPU PLL CPU M CPU N CPU N SRC PLL
SRC N
SRC N
divider (not DEFAULT allowable
Gear
divider DEFA
ULT allowable
Gear
Constants
range for Constants changeable
range for
by user)
DAF
DAF
(G)
FSEL_3
FSEL_2
FSEL_1
FSEL_0
(MHz)
(MHz)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
X
1
0
0
0
0
1
1
1
0
0
0
0
1
1
HIGH
HIGH
0
0
1
1
0
0
1
0
0
1
1
0
0
1
LOW
HIGH
1
1
1
0
0
0
0
1
1
1
0
0
0
0
X
X
100
133.3333333
166.6666667
200
266.6666667
333.3333333
400
100.952381
133.968254
167
200.952381
266.6666667
334
400.6451613
Tristate
REF/N
100
100
100
100
100
100
100
100
100
100
100
100
100
100
Tristate
REF/N
30
40
60
60
80
120
120
30
40
60
60
80
120
120
Tristate
REF/N
60
60
63
60
60
63
60
63
63
60
63
60
60
62
Tristate
REF/N
200
200
175
200
200
175
200
212
211
167
211
200
167
207
Tristate
REF/N
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
Tristate
REF/N
30
30
30
30
30
30
30
30
30
30
30
30
30
30
60
60
60
60
60
60
60
60
60
60
60
60
60
60
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 167 - 266
200 167 - 266
Figure 1. CPU and SRC Frequency Select Tables
Rev 1.0, November 20, 2006
Page 3 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
