256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
CE#
OE#
OE#/V
PP
V
PP
V
DD
V
SS
NC
Pin Name
Address Inputs
Data Input/output
Chip Enable
Output Enable
Output Enable/V
PP
Power Supply for
Program or Erase
Power Supply
Ground
No Connection
Unconnected pins.
T2.3 502
Functions
To provide memory addresses
To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low
For SST27SF256/010/020, to gate the data output buffers during Read operation
For SST27SF512, to gate the data output buffers during Read operation and high voltage
pin during Chip-Erase and programming operation
For SST27SF256/010/020, high voltage pin during Chip-Erase and programming opera-
tion 12V (±5%)
To provide 5.0V supply (±10%)
1. A
MS
= Most significant address
A
MS
= A
14
for SST27SF256, A
15
for SST27SF512, A
16
for SST27SF010, and A
17
for SST27SF020
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01
502
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
