1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
Note
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
Note: Toggle bit output is always high first.
1147 F07.1
A
A
= Most significant address
MS
MS
= A for SST39SF010A, A for SST39SF020A, and A for SST39SF040
16 17 18
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555 5555 2AAA
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW0
SW5
1147 F08.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 10)
SA = Sector Address
X
A
A
= Most significant address
MS
MS
= A for SST39SF010A, A for SST39SF020A, and A for SST39SF040
16 17 18
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71147-06-000
8/04
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
