1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
TABLE 5: DC O
PERATING
C
HARACTERISTICS
V
DD
= 4.5-5.5V
1
Limits
Symbol
I
DD
Parameter
Power Supply Current
Read
2
Program and Erase
I
SB1
I
SB2
I
LI
I
LO
V
IL
V
IH
V
IHC
V
OL
V
OH
Standby V
DD
Current
(TTL input)
Standby V
DD
Current
(CMOS input)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
2.4
2.0
V
DD
-0.3
0.4
25
35
3
100
1
10
0.8
mA
mA
mA
µA
µA
µA
V
V
V
V
V
Min
Max
Units
Test Conditions
Address input=V
ILT
/V
IHT
, at f=1/T
RC
Min
V
DD
=V
DD
Max
CE#=V
IL
, OE#=WE#=V
IH
, all I/Os open
CE#=WE#=V
IL
, OE#=V
IH
CE#=V
IH
, V
DD
=V
DD
Max
CE#=V
IHC
, V
DD
=V
DD
Max
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
DD
=V
DD
Min
V
DD
=V
DD
Max
V
DD
=V
DD
Max
I
OL
=2.1 mA, V
DD
=V
DD
Min
I
OH
=-400 µA, V
DD
=V
DD
Min
T5.10 1147
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and V
DD
= 5V for SF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the
Multi-Purpose Flash Power Rating
application note for further information.
TABLE 6: R
ECOMMENDED
S
YSTEM
P
OWER
-
UP
T
IMINGS
Symbol
T
PU-READ1
T
PU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Program/Erase Operation
Minimum
100
100
Units
µs
µs
T6.1 1147
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: C
APACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
C
I/O1
C
IN
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
12 pF
6 pF
T7.0 1147
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: R
ELIABILITY
C
HARACTERISTICS
Symbol
N
END
T
DR1
I
LTH1
1,2
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
10,000
100
100 + I
DD
Units
Cycles
Years
mA
Test Method
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
T8.2 1147
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. N
END
endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2003 Silicon Storage Technology, Inc.
S71147-06-000
8/04
8
SST [ SILICON STORAGE TECHNOLOGY, INC ]
