4 Mbit LPC Flash
SST49LF040
Advance Information
Data# Polling (DQ
7
)
When the SST49LF040 device is in the internal Program
operation, any attempt to read DQ
7
will produce the com-
plement of the true data. Once the Program operation is
completed, DQ
7
will produce true data. Note that even
though DQ
7
may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ
7
will produce a ‘0’. Once the
internal Erase operation is completed, DQ
7
will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# pulse. See Figure 21 for the Data# Polling tim-
ing diagram and Figure 36 for a flowchart. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# pulse
for Program operation. For Sector-, Block-, or Chip-Erase,
the Toggle Bit is valid after the rising edge of sixth WE#
pulse. See Figure 22 for the Toggle Bit timing diagram and
Software Data Protection (SDP)
The SST49LF040 provides the JEDEC approved Software
Data Protection scheme for all data alteration operation,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three-byte sequence. The three-
byte load sequence is used to initiate the Program opera-
tion, providing optimal protection from inadvertent Write
operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of a six-
byte load sequence. The SST49LF040 device is shipped
with the Software Data Protection permanently enabled.
See Table 8 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to Read mode, within T
RC.
Electrical Specifications
The AC and DC specifications for the LPC interface sig-
nals (LA0[3:0], LFRAME, LCLCK and RST#) as defined
in Section 4.2.2.4 of the PCI local Bus specification, Rev.
2.1. Refer to Table 9 for the DC voltage and current spec-
ifications. Refer to Tables 13 through 16 and Tables 19
through 21 for the AC timing specifications for Clock,
Read, Write, and Reset operations.
Product Identification
The Product Identification mode identifies the device as the
SST49LF040 and manufacturer as SST.
TABLE 6: P
RODUCT
I
DENTIFICATION
Address
Manufacturer’s ID
Device ID
SST49LF040
0001H
51H
T6.1 562
Data
BFH
Data Protection
The SST49LF040 device provides both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
0000H
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between V
DD
and
V
SS
less than 1 cm away from the V
DD
pin of the device.
Additionally, a low frequency 4.7 µF electrolytic capacitor
from V
DD
to V
SS
should be placed within 5 cm of the V
DD
pin. If you use a socket for programming purposes add an
additional 1-10 µF next to each socket.
The RST# pin must remain stable at V
IH
for the entire dura-
tion of an Erase operation. WP# must remain stable at V
IH
for the entire duration of the Erase and Program operations
for non-boot block sectors. To write data to the top boot
block sectors, the TBL# pin must also remain stable at V
IH
for the entire duration of the Erase and Program operations.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
15
SST [ SILICON STORAGE TECHNOLOGY, INC ]
