4 Mbit LPC Flash
SST49LF040
Advance Information
TCYC
LCLK
CE#
RST#
LFRAME#
Start
Memory
Read
Cycle
010Xb
Address
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12]
Load Address in 8 Clocks
A[11:8]
A[7:4]
A[3:0]
1111b
TAR
Tri-State
TVAL
Sync
0000b
TSU TDH
Data
Next Start
D[7:4]
TAR
0000b
1 Clock
LAD[3:0]
0000b
D[3:0]
1 Clock 1 Clock
2 Clocks
1 Clock Data Out 2 Clocks
562 ILL F09.0
FIGURE 10: R
EAD
C
YCLE
T
IMING
D
IAGRAM
(LPC M
ODE
)
TCYC
LCLK
CE#
RST#
LFRAME#
Start
Memory
Write
Cycle
011Xb
Address
A[31:28] A[27:24] A[23:20]
A[19:16] A[15:12]
Load Address in 8 Clocks
A[11:8]
A[7:4]
A[3:0]
TSU TDH
Data
D[3:0]
D[7:4]
TAR
1111b Tri-State
2 Clocks
Sync
0000b
1 Clock
TAR
Next Start
0000b
1 Clock
562 ILL F10.0
LAD[3:0]
0000b
1 Clock 1 Clock
Load Data in 2 Clocks
FIGURE 11: W
RITE
C
YCLE
T
IMING
D
IAGRAM
(LPC M
ODE
)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
23
SST [ SILICON STORAGE TECHNOLOGY, INC ]
