4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 14: R
ESET
T
IMING
P
ARAMETERS
(LPC M
ODE
), V
DD
=3.0-3.6V
Symbol
T
PRST
T
KRST
T
RSTP
T
RSTF
T
RST1
T
RSTE
Parameter
V
DD
stable to Reset Low
Clock Stable to Reset Low
RST# Pulse Width
RST# Low to Output Float
RST# High to LFRAME# Low
RST# Low to reset during Sector-/Block-Erase or Program
1
10
Min
1
100
100
48
Max
Units
ms
µs
ns
ns
µs
µs
T14.0 562
1. There will be a latency of T
RSTE
if a reset procedure is performed during a programming or erase operation,
V
DD
CLK
T
PRST
T
KRST
RST#/INIT#
T
RSTP
T
RSTE
T
RSTF
LAD[3:0]
T
RST
Sector-/Block-Erase
or Program operation
aborted
LFRAME#
562 ILL F06.0
FIGURE 7: R
ESET
T
IMING
D
IAGRAM
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
19
SST [ SILICON STORAGE TECHNOLOGY, INC ]
