4 Mbit LPC Flash
SST49LF040
Advance Information
LCLK
RST#
CE#
LFRAME#
Memory
Write
Cycle
A[31:28] A[27:24] A[23:20]
Start next
Command
0000b
1 Clock
LAD[3:0]
1st Start
Address1
A[19:16]
A[15:12]
A[11:8]
A[7:4]
A[3:0]
D[3:0]
Data
Dn[7:4]
TAR
1111b Tri-State
2 Clocks
Sync
0000b
1 Clock
TAR
0000b 011Xb
1 Clock 1 Clock
Load Address in 8 Clocks
Load Data in 2 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Memory
Read
Cycle
010Xb
A[31:28] A[27:24] A[23:20]
Next start
Address1
A[19:16]
A[15:12]
A[11:8]
A[7:4]
A[3:0]
TAR
1111b
Sync
Data
XXXXb
D7#,xxx
TAR
0000b
1 Clock
Tri-State 0000b
1 Clock
LAD[3:0]
Start
0000b
1 Clock 1 Clock
2 Clocks
Load Address in 8 Clocks
Read the DQ7 to see if internal write complete or not.
Data out 2 Clocks
LCLK
RST# = VIH
CE# = VIL
LFRAME#
Start
0000b
Memory
Read
Cycle
010Xb
A[31:28] A[27:24] A[23:20]
Next start
Address1
A[19:16]
A[15:12]
A[11:8]
A[7:4]
A[3:0]
TAR
1111b Tri-State
2 Clocks
Sync
0000b
Data
XXXXb
D7,xxx
TAR
0000b
1 Clock
LAD[3:0]
1 Clock 1 Clock
Load Address in 8 Clocks
When internal write complete, the DQ7 will equal to D7.
1 Clock Data out 2 Clocks
562 ILL F12.1
Note: YYYY must be within memory address range specified in Figures 4 and 5.
FIGURE 13: D
ATA
# P
OLLING
T
IMING
D
IAGRAM
(LPC M
ODE
)
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
25
SST [ SILICON STORAGE TECHNOLOGY, INC ]
