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M29F400BB90N1T 参数 Datasheet PDF下载

M29F400BB90N1T图片预览
型号: M29F400BB90N1T
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位512KB ×8或256Kb的X16 ,引导块单电源闪存 [4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 22 页 / 201 K
品牌: STMICROELECTRONICS [ ST ]
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M29F400BT, M29F400BB  
The Block Protection Status of each block can be  
Unlock Bypass Program Command. The Un-  
lock Bypass Program command can be used to  
program one address in memory at a time. The  
command requires two Bus Write operations, the  
final write operation latches the address and data  
in the internal state machine and starts the Pro-  
gram/Erase Controller.  
read using a Bus Read operation with A0 = V ,  
IL  
A1 = V , and A12-A17 specifying the address of  
IH  
the block. The other address bits may be set to ei-  
ther V or V . If the addressed block is protected  
IL  
IH  
then 01h is output on Data Inputs/Outputs DQ0-  
DQ7, otherwise 00h is output.  
Program Command. The Program command  
can be used to program a value to one address in  
the memory array at a time. The command re-  
quires four Bus Write operations, the final write op-  
eration latches the address and data in the internal  
state machine and starts the Program/Erase Con-  
troller.  
If the address falls in a protected block then the  
Program command is ignored, the data remains  
unchanged. The Status Register is never read and  
no error condition is given.  
During the program operation the memory will ig-  
nore all commands. It is not possible to issue any  
command to abort or pause the operation. Typical  
program times are given in Table 9. Bus Read op-  
erations during the program operation will output  
the Status Register on the Data Inputs/Outputs.  
See the section on the Status Register for more  
details.  
The Program operation using the Unlock Bypass  
Program command behaves identically to the Pro-  
gram operation using the Program command. A  
protected block cannot be programmed; the oper-  
ation cannot be aborted and the Status Register is  
read. Errors must be reset using the Read/Reset  
command, which leaves the device in Unlock By-  
pass Mode. See the Program command for details  
on the behavior.  
Unlock Bypass Reset Command. The Unlock  
Bypass Reset command can be used to return to  
Read/Reset mode from Unlock Bypass Mode.  
Two Bus Write operations are required to issue the  
Unlock Bypass Reset command.  
Chip Erase Command. The Chip Erase com-  
mand can be used to erase the entire chip. Six Bus  
Write operations are required to issue the Chip  
Erase Command and start the Program/Erase  
Controller.  
After the program operation has completed the  
memory will return to the Read mode, unless an  
error has occurred. When an error occurs the  
memory will continue to output the Status Regis-  
ter. A Read/Reset command must be issued to re-  
set the error condition and return to Read mode.  
If any blocks are protected then these are ignored  
and all the other blocks are erased. If all of the  
blocks are protected the Chip Erase operation ap-  
pears to start but will terminate within about 100µs,  
leaving the data unchanged. No error condition is  
given when protected blocks are ignored.  
Note that the Program command cannot change a  
bit set at ’0’ back to ’1’. One of the Erase Com-  
mands must be used to set all the bits in a block or  
in the whole memory from ’0’ to ’1’.  
Unlock Bypass Command. The Unlock Bypass  
command is used in conjunction with the Unlock  
Bypass Program command to program the memo-  
ry. When the access time to the device is long (as  
with some EPROM programmers) considerable  
time saving can be made by using these com-  
mands. Three Bus Write operations are required  
to issue the Unlock Bypass command.  
Once the Unlock Bypass command has been is-  
sued the memory will only accept the Unlock By-  
pass Program command and the Unlock Bypass  
Reset command. The memory can be read as if in  
Read mode.  
During the erase operation the memory will ignore  
all commands. It is not possible to issue any com-  
mand to abort the operation. Typical chip erase  
times are given in Table 9. All Bus Read opera-  
tions during the Chip Erase operation will output  
the Status Register on the Data Inputs/Outputs.  
See the section on the Status Register for more  
details.  
After the Chip Erase operation has completed the  
memory will return to the Read Mode, unless an  
error has occurred. When an error occurs the  
memory will continue to output the Status Regis-  
ter. A Read/Reset command must be issued to re-  
set the error condition and return to Read Mode.  
The Chip Erase Command sets all of the bits in un-  
protected blocks of the memory to ’1’. All previous  
data is lost.  
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