M29F400BT, M29F400BB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
ID
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteris-
tics.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, V . When BYTE is Low, V , these pins
IH
IL
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
During Program or Erase operations Ready/Busy
is Low, V . Ready/Busy will remain Low during
OL
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
Data Input/Output or Address Input (DQ15A-1).
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
When BYTE is High, V , this pin behaves as a
IH
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V , this pin behaves as an address
IL
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Byte/Word Organization Select (BYTE). The Byte/
Word Organization Select pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When Byte/Word Organization Select is Low,
V , the memory is in 8-bit mode, when it is High,
IL
V , the memory is in 16-bit mode.
IH
V
Supply Voltage. The V
Supply Voltage
CC
CC
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
High, V , all other pins are ignored.
IH
Supply Voltage is less than the Lockout Voltage,
V . This prevents Bus Write operations from ac-
LKO
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all Blocks that have been pro-
tected.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CC
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
A Hardware Reset is achieved by holding Reset/
erase operations, I
.
CC4
Block Temporary Unprotect Low, V , for at least
IL
Vss Ground. The V
Ground is the reference
SS
t
. After Reset/Block Temporary Unprotect
PLPX
for all voltage measurements.
goes High, V , the memory will be ready for Bus
IH
Read and Bus Write operations after t
or
PHEL
4/22
STMICROELECTRONICS [ ST ]
