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M29F400BB90N1T 参数 Datasheet PDF下载

M29F400BB90N1T图片预览
型号: M29F400BB90N1T
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位512KB ×8或256Kb的X16 ,引导块单电源闪存 [4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 22 页 / 201 K
品牌: STMICROELECTRONICS [ ST ]
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M29F400BT, M29F400BB  
BUS OPERATIONS  
mand Interface on the rising edge of Chip Enable  
or Write Enable, whichever occurs first. Output En-  
There are five standard bus operations that control  
the device. These are Bus Read, Bus Write, Out-  
put Disable, Standby and Automatic Standby. See  
Tables 5 and 6, Bus Operations, for a summary.  
Typically glitches of less than 5ns on Chip Enable  
or Write Enable are ignored by the memory and do  
not affect bus operations.  
able must remain High, V , during the whole Bus  
IH  
Write operation. See Figures 9 and 10, Write AC  
Waveforms, and Tables 15 and 16, Write AC  
Characteristics, for details of the timing require-  
ments.  
Output Disable. The Data Inputs/Outputs are in  
the high impedance state when Output Enable is  
Bus Read. Bus Read operations read from the  
memory cells, or specific registers in the Com-  
mand Interface. A valid Bus Read operation in-  
volves setting the desired address on the Address  
High, V .  
IH  
Standby. When Chip Enable is High, V , the  
IH  
Data Inputs/Outputs pins are placed in the high-  
impedance state and the Supply Current is re-  
duced to the Standby level.  
Inputs, applying a Low signal, V , to Chip Enable  
IL  
and Output Enable and keeping Write Enable  
High, V . The Data Inputs/Outputs will output the  
IH  
When Chip Enable is at V the Supply Current is  
IH  
value, see Figure 8, Read Mode AC Waveforms,  
and Table 14, Read AC Characteristics, for details  
of when the output becomes valid.  
reduced to the TTL Standby Supply Current, I  
.
CC2  
To further reduce the Supply Current to the CMOS  
Standby Supply Current, I , Chip Enable should  
CC3  
Bus Write. Bus Write operations write to the  
Command Interface. A valid Bus Write operation  
begins by setting the desired address on the Ad-  
dress Inputs. The Address Inputs are latched by  
the Command Interface on the falling edge of Chip  
Enable or Write Enable, whichever occurs last.  
The Data Inputs/Outputs are latched by the Com-  
be held within V  
levels see Table 13, DC Characteristics.  
During program or erase operations the memory  
will continue to use the Program/Erase Supply  
± 0.2V. For Standby current  
CC  
Current, I  
, for Program or Erase operations un-  
CC4  
til the operation completes.  
Table 5. Bus Operations, BYTE = V  
IL  
Data Inputs/Outputs  
Address Inputs  
DQ15A–1, A0-A17  
Operation  
E
G
W
DQ14-DQ8  
Hi-Z  
DQ7-DQ0  
Data Output  
Data Input  
Hi-Z  
V
IL  
V
V
IH  
Bus Read  
Cell Address  
IL  
IH  
IH  
V
IL  
V
V
V
V
Bus Write  
Command Address  
Hi-Z  
IL  
Output Disable  
Standby  
X
X
Hi-Z  
IH  
V
X
X
X
Hi-Z  
Hi-Z  
IH  
A0 = V , A1 = V , A9 = V ,  
Read Manufacturer  
Code  
IL  
IL  
ID  
V
V
V
V
V
Hi-Z  
Hi-Z  
20h  
IL  
IL  
IL  
IL  
IH  
IH  
Others V or V  
IL  
IH  
A0 = V , A1 = V , A9 = V ,  
D5h (M29F400BT)  
D6h (M29F400BB)  
IH  
IL  
ID  
V
Read Device Code  
Others V or V  
IL  
IH  
Note: X = V or V  
.
IH  
IL  
Table 6. Bus Operations, BYTE = V  
IH  
Address Inputs  
A0-A17  
Data Inputs/Outputs  
Operation  
Bus Read  
E
G
W
DQ15A–1, DQ14-DQ0  
Data Output  
Data Input  
Hi-Z  
V
IL  
V
V
Cell Address  
IL  
IH  
IH  
IH  
V
IL  
V
V
V
V
Bus Write  
Command Address  
IL  
Output Disable  
Standby  
X
X
X
IH  
V
X
X
Hi-Z  
IH  
A0 = V , A1 = V , A9 = V ,  
Read Manufacturer  
Code  
IL  
IL  
ID  
V
V
V
V
V
0020h  
IL  
IL  
IL  
IL  
IH  
IH  
Others V or V  
IL  
IH  
A0 = V , A1 = V , A9 = V ,  
00D5h (M29F400BT)  
00D6h (M29F400BB)  
IH  
IL  
ID  
V
Read Device Code  
Others V or V  
IL  
IH  
Note: X = V or V  
.
IH  
IL  
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