SM5964B
8-Bit Micro-controller
64KB with ISP Flash
& 1KB RAM embedded
signal has been received after the complete 8-bit data transmit on the bus.
(Read only)
MST: Set 1 to force working at TWSI master mode.
TXACK: The acknowledge bit for response to transmitter or master addressing. When
receiving complete 8-bit data, setting this bit to respond with NACK otherwise
ACK is responded.
Mnemonic: TWSIA
7
6
ADR.6
ADR.5
Address: C1h
0
Reset
ADRMK
A0h
5
ADR.4
4
ADR.3
3
ADR.2
2
ADR.1
1
ADR.0
ADR[6:0]: These 7 bits define slave address on the TWSI/IIC bus.
ADRMK: Address Mask bit. Its only compare 4 bits MSB when set this bit. When this bit
is set, ADR.2 – ADR.0 is masked to excluded from the address comparison. In
other words, it will be addressed “hit” and respond with ACK as long as ADR6-
ADR.3 is matched.
Mnemonic: TWSIC1
7
6
TWSIE
-
Address: C2h
0
Reset
TWSIFS0
01h
5
-
4
-
3
BusBusy
2
TWSIFS2
1
TWSIFS1
TWSIE: TWSI function enable bit.
BusBusy: When TWSI bus is detected with “START” condition, this bit is set. When
TWSI bus is detected with “STOP” condition, this bit is cleared. (Read only)
TWSIFS[2:0]: TWSI clock rate selector at Master mode.
TWSIFS[2:0]
000
001
010
011
100
101
110
111
Mnemonic: TWSIC2
7
6
MATCH
SRW
SCL Frequency
Xtal/32
Xtal/64 (default)
Xtal/128
Xtal/256
Xtal/512
Xtal/1024
Xtal/2048
Xtal/4096
Address: C3h
0
Reset
MRW
00h
5
-
4
-
3
RESTART
2
-
1
-
MATCH: When the first received data (following the START signal) in TWSIRXD register
is matches with the address that address register (TWSIA) set, this bit will set.
(Read only & Slave mode only)
SRW: The slave mode read (received) or wrote (transmit) on the TWSI bus. When
this bit is set, the slave module transmit data on the TWSI bus (SDA). When
this bit is clear, the slave module received data on the TWSI bus (SDA). (Read
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M081
Ver A SM5964B 3/7/2014
- 47 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
