SyncMOS Technologies Inc.
January 2003
Pin Descriptions
40L
44L
44L
PDIP QFP PLCC
Symbol
Pin# Pin# Pin#
1
40
2
P1.0/T2
2
41
3
P1.1/T2EX
3
42
4
P1.2/SPWM
4
43
5
P1.3
5
44
6
P1.4
6
1
7
P1.5/PWM
7
2
8
P1.6
8
3
9
P1.7
9
4
10
RES
10
5
11
P3.0/RXD
11
7
13
P3.1/TXD
12
8
14
P3.2/#INT0
13
9
15
P3.3/#INT1
14
10
16
P3.4/T0/ADC0
15
11
17
P3.5/T1/ADC1
16
12
18
P3.6/#WR/ADC2
17
13
19
P3.7/#RD/ADC3
18
14
20
XTAL2
19
15
21
XTAL1
20
16
22
VSS
21
18
24
P2.0/A8/COM0
22
19
25
P2.1/A9/COM1
23
20
26
P2.2/A10/COM2
24
21
27
P2.3/A11/COM3
25
22
28
P2.4/A12/SEG0
26
23
29
P2.5/SEG1
27
24
30
P2.6/SEG2
28
25
31
P2.7/SEG3
29
26
32
#PSEN/SEG4
30
27
33
ALE/SEG5
31
29
35
#EA
32
30
36
P0.7/AD7/SEG6
33
31
37
P0.6/AD6/SEG7
34
32
38
P0.5/AD5/SEG8
35
33
39
P0.4/AD4/SEG9
36
34
40
P0.3/AD3/SEG10
37
35
41
P0.2/AD2/SEG11
38
36
42
P0.1/AD1/SEG12
39
37
43
P0.0/AD0/SEG13
40
38
44
VDD
17
23 P4.0
28
34 P4.1
39
1 P4.2
6
12 P4.3
Active
I/O
(GPIO)
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
Names
Preliminary
SM79108
H
-/L
-/L
L
bit 0 of port 1 & timer 2 clock out
bit 1 of port 1 & timer 2 control
bit 2 of port 1 & SPWM channel
bit 3 of port 1
bit 4 of port 1
bit 5 of port 1 & PWM channel
bit 6 of port 1
bit 7 of port 1
Reset
bit 0 of port 3 & receive data
bit 1 of port 3 & transmit data
bit 2 of port 3 & low true interrupt 0
bit 3 of port 3 & low true interrupt 1
bit 4 of port 3 & ADC channel 0 & Timer 0
bit 5 of port 3 & ADC channel 1 &Timer 1
bit 6 of port 3 & ADC channel 2 & external memory write
bit 7 of port 3 & ADC channel 3 & external memory read
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of external memory address & LCCD common 0 output
bit 1 of port 2 & bit 9 of external memory address & LCCD common 1 output
bit 2 of port 2 & bit 10 of external memory address & LCCD common 2 output
bit 3 of port 2 & bit 11 of external memory address & LCCD common 3 output
bit 4 of port 2 & bit 12 of external memory address & LCCD seg 0 output
bit 5 of port 2 & LCCD seg 1 output
bit 6 of port 2 & LCCD seg 2 output
bit 7 of port 2 & LCCD seg 3 output
program storage enable & LCCD seg 4 output
address latch enable & LCCD seg 5 output
external access
bit 7 of port 0 & data/address bit 7 of external memory & LCCD seg 6 output
bit 6 of port 0 & data/address bit 6 of external memory & LCCD seg7 output
bit 5 of port 0 & data/address bit 5 of external memory & LCCD seg 8 output
bit 4 of port 0 & data/address bit 4 of external memory & LCCD seg 9 output
bit 3 of port 0 & data/address bit 3 of external memory & LCCD seg 10 output
bit 2 of port 0 & data/address bit 2 of external memory & LCCD seg 11 output
bit 1 of port 0 & data/address bit 1 of external memory & LCCD seg 12 output
bit 0 of port 0 & data/address bit 0 of external memory & LCCD seg 13 output
Drive Voltage, Vcc
bit 0 of Port 4
bit 1 of Port 4
bit 2 of Port 4
bit 3 of Port 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/26
Preliminary
Ver 1.0
SM79108 01/03
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
