73S8024RN Data Sheet
DS_8024RN_020
8 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the
CMDVCC
high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V
DD
fault, V
PC
fault, V
CC
fault,
and card extraction during the session. To be noted that V
PC
and V
CC
faults are linked together so that a
fault is generated when V
PC
goes lower than V
CC
.
The following steps show the deactivation sequence and the timing of the card control signals when the
system controller sets the
CMDVCC
high or
OFF
goes low due to a fault or card removal:
•
•
•
•
RST goes low at the end of t
1
.
CLK is set low at the end of t
2
.
I/O goes low at the end of t
3
. Out of reception mode.
V
CC
is shut down at the end of time t
4
. After a delay t
5
(discharge of the V
CC
capacitor), V
CC
is low.
CMDVCC
OFF
-- OR --
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
t
1
=
t
2
=
t
3
=
t
4
=
t
5
=
> 0.5μs, timing by 1.5MHz internal Oscillator
> 7.5μs
> 0.5μs
> 0.5μs
depends on V
CC
filter capacitor.
For NDS application, C
F
=1μF makes t
1
+ t
2
+ t
3
+ t
4
+ t
5
< 100μs
Figure 4: Deactivation Sequence
12
Rev. 1.8
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
