DS_8024RN_020
73S8024RN Data Sheet
11 Typical Application Schematic
AUX2UC_to/from_uC
AUX1UC_to.from_uC
VDD
See NOTE 6
See NOTE 3
I/OUC_to/from_uC
See NOTE 5
CLKDIV1_from_uC
CLKDIV2_from_uC
5V/3V_select_from_uC
VDD
- OR -
C4
100nF
C5
10uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLKDIV1
CLKDIV2
5V3V_
GND
NC
VPC
CLKSTOP
CLKLVL
PRESB
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
OFF_
GND
VDD
RSTIN
CMDVCC_
VDDF_ADJ
VCC
RST
CLK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R3
Rext2
External_clock_from uC
VPC
See NOTE 2
C2
22pF
C3
22pF
VDD
See NOTE 1
C6
100nF
R1
Rext1
Y1
CRYSTAL
CLKSTOP_from_uC
CLKLVL_from_uC
See NOTE 5
See NOTE 4
73S8024RN
SO28
See note 7
OFF_interrupt_to_uC
RSTIN_from_uC
VDD
R2
NOTES:
Card detection
1) VDD = 2.7V to 5.5V DC.
20K
switch is
normally closed
2) VPC = 4.75V(EMV, ISO)/4.85(NDS) to 5.5V DC
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6)Internal pull-up allows it to be left open if unused.
7) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
NDS & ISO7816=1uF, EMV=3.3uF
Low ESR (<100mohms) C1
C1
should be placed near the SC
connecter contact
C8
I/O
VPP
GND
C4
CLK
RST
VCC
8
7
6
5
4
3
2
1
CMDVCC_from_uC
SW-2
SW-1
10
9
CLK track should be routed
far from RST, I/O, C4 and
C8.
Smart Card Connector
Figure 8: 73S8024RN – Typical Application Schematic
Rev. 1.8
15
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
