78M6612 Data Sheet
DS_6612_001
Port Registers:
The I/O ports are controlled by Special Function Registers
P0, P1,
and
P2.
The contents
of the SFR can be observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see
causes the corresponding pin to be at high level (V3P3), and writing a ‘0’ causes the
corresponding pin to be held at low level (GND). The data direction registers
DIR0, DIR1,
and
DIR2
define individual pins as input or output pins (see the
for details).
Table 9: Port Registers
Register
P0
DIR0
P1
DIR1
P2
DIR2
SFR
Address
0x80
0xA2
0x90
0x91
0xA0
0xA1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Register for port 0 read and write operations (pins DIO4…DIO7).
Data direction register for port 0. Setting a bit to 1 means that the
corresponding pin is an output.
Register for port 1 read and write operations (pins DIO8…DIO11,
DIO14-DIO15).
Data direction register for port 1.
Register for port 2 read and write operations (pins DIO16…DIO17,
DIO19…DIO21).
Data direction register for port 2.
All DIO ports on the chip are bi-directional. Each consists of a Latch (SFR
P0
to
P2),
an output driver,
and an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO
pin is configured as an output, the state of the pin can still be read by the MPU, for example when
counting pulses issued via DIO pins that are under CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as
outputs, can be used to implement pulse counting.
1.4.4 Special Function Registers Specific to the 78M6612
shows the location and description of the 78M6612-specific SFRs.
Table 10: Special Function Registers
Register
ERASE
Alternative
Name
FLSH_ERASE
SFR
Address
0x94
R/W
W
Description
This register is used to initiate either the Flash Mass
Erase cycle or the Flash Page Erase cycle. Specific
patterns are expected for
FLSH_ERASE
in order to initiate
the appropriate Erase cycle (default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be
preceded by a write to
FLSH_PGADR
@ SFR
0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be
preceded by a write to
FLSH_MEEN
@ SFR
0xB2 and the debug port must be enabled.
Any other pattern written to
FLSH_ERASE
will have no
effect.
Flash Page Erase Address register containing the Flash
memory page address (page 0 through 127) that will be
erased during the Page Erase cycle (default = 0x00).
Rev. 1.2
FPAG
FLSH_PGADR
0xB7
R/W
22
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