ADC12D1000, ADC12D1600
SNAS480M –MAY 2010–REVISED MARCH 2013
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Ball Descriptions and Equivalent Circuits
Table 1. Analog Front-End and Clock Balls
Ball No.
Name
Equivalent Circuit
Description
Differential signal I- and Q-inputs. In the Non-Dual
Edge Sampling (Non-DES) Mode, each I- and Q-
input is sampled and converted by its respective
channel with each positive transition of the CLK
input. In Non-ECM (Non-Extended Control Mode)
and DES Mode, both channels sample the I-input.
In Extended Control Mode (ECM), the Q-input
may optionally be selected for conversion in DES
Mode by the DEQ Bit (Addr: 0h, Bit 6).
V
A
50k
Each I- and Q-channel input has an internal
common mode bias that is disabled when DC-
coupled Mode is selected. Both inputs must be
either AC- or DC-coupled. The coupling mode is
selected by the VCMO Pin.
AGND
100
V
CMO
H1/J1
N1/M1
VinI+/-
VinQ+/-
Control from V
CMO
V
A
In Non-ECM, the full-scale range of these inputs is
determined by the FSR Pin; both I- and Q-
channels have the same full-scale input range. In
ECM, the full-scale input range of the I- and Q-
channel inputs may be independently set via the
Control Register (Addr: 3h and Addr: Bh). Note
that the high and low full-scale input range setting
in Non-ECM corresponds to the mid and minimum
full-scale input range in ECM.
50k
AGND
The input offset may also be adjusted in ECM.
V
A
Differential Converter Sampling Clock. In the Non-
DES Mode, the analog inputs are sampled on the
positive transitions of this clock signal. In the DES
Mode, the selected input is sampled on both
transitions of this clock. This clock must be AC-
coupled.
50k
50k
AGND
U2/V1
CLK+/-
100
V
BIAS
V
A
AGND
V
A
Differential DCLK Reset. A positive pulse on this
input is used to reset the DCLKI and DCLKQ
outputs of two or more ADC12D1000/1600s in
order to synchronize them with other
ADC12D1000/1600s in the system. DCLKI and
DCLKQ are always in phase with each other,
unless one channel is powered down, and do not
require a pulse from DCLK_RST to become
synchronized. The pulse applied here must meet
timing relationships with respect to the CLK input.
Although supported, this feature has been
superseded by AutoSync.
AGND
V2/W1
DCLK_RST+/-
100
V
A
AGND
4
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