W25Q16V
10.2.14 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the four dummy
clocks are not required, which further reduces the instruction overhead allowing even faster random
access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable
the Octal Word Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 14a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits (M7-0) equals “Ax” hex, then the next Octal Word Read Quad I/O
instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in
figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be
immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits (M7-0) are any value
other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte
instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can
be used to reset (M7-0) before issuing normal instructions (See 10.2.29 for detailed descriptions).
Instruction (E3h)
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
Byte 1
Byte 2
Byte 3
Byte 4
Figure 14a. Octal Word Read Quad I/O Instruction Sequence (M7-0 = 0xh or NOT Axh)
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