W39V080A
14. TIMING WAVEFORMS FOR LPC INTERFACE MODE
14.1 Read Cycle Timing Diagram
T
CYC
CLK
#RESET
#LFRAME
Memory
Read
Cycle
T
KQ
Start
Address
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
TAR
1111b
Sync
T
SU
T
HD
Data
D[3:0]
D[7:4]
TAR
Next Start
0000b
LAD[3:0]
0000b 010Xb
1 Clock 1 Clock
Tri-State 0000b
1 Clock
2 Clocks
Data out 2 Clocks
1 Clock
14.2 Write Cycle Timing Diagram
TCYC
CLK
#RESET
#LFRAME
Start
LAD[3:0]
Memory
Write
Cycle
Address
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12]
Load Address in 8 Clocks
A[11:8]
A[7:4]
A[3:0]
TSU THD
Data
D[3:0]
D[7:4]
TAR
1111b
Tri-State
Sync
0000b
1 Clock
TAR
Next Start
0000b
1 Clock
0000b 011Xb
1 Clock 1 Clock
Load Data in 2 Clocks
2 Clocks
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Publication Release Date: Dec. 28, 2005
Revision A4
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