Production Data
WM8150
MCLK
VSMP
TIMING CONTROL
CL
R
S
V
S
FROM CONTROL
INTERFACE
C
IN
S/H
+
VINP
1
RLC
2
+
S/H
-
INPUT SAMPLING
BLOCK
TO OFFSET DAC
CDS
EXTERNAL VRLC
VRLC/
VBIAS
4-BIT
RLC DAC
VRLCEXT
CDS
FROM CONTROL
INTERFACE
Figure 4 Reset Level Clamping and CDS Circuitry
Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the
RLCINT bit for a typical CCD waveform, with CL applied during the reset period.
The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP
pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on
the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6).
MCLK
VSMP
ACYC/RLC
or RLCINT
1
X
Programmable Delay
X
0
X
X
0
CL
(CDSREF = 01)
INPUT VIDEO
RGB
RGB
RLC on this Pixel
RGB
No RLC on this Pixel
Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
s
/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 6.
w
PD Rev 3.0 November 2002
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
