WM8150
INPUT VIDEO SAMPLING
t
PER
MCLK
t
VSMPSU
VSMP
INPUT
t
VSU
VIDEO
t
VH
t
RSU
t
RH
t
VSMPH
t
MCLKH
t
MCLKL
Production Data
Figure 1 Input Video Timing
Note:
1.
See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, T
A
= 25°C, MCLK = 16MHz unless otherwise stated.
PARAMETER
MCLK period
MCLK high period
MCLK low period
VSMP set-up time
VSMP hold time
Video level set-up time
Video level hold time
Reset level set-up time
Reset level hold time
Notes:
1.
2.
t
VSU
and t
RSU
denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
SYMBOL
t
PER
t
MCLKH
t
MCLKL
t
VSMPSU
t
VSMPH
t
VSU
t
VH
t
RSU
t
RH
TEST CONDITIONS
MIN
62.5
28.1
28.1
8
4
15
5
15
5
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT DATA TIMING
MCLK
t
PD
t
PD
OP[3:0]
Figure 2 Output Data Timing
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, T
A
= 25°C, MCLK = 16MHz unless otherwise stated.
PARAMETER
Output propagation delay
SYMBOL
t
PD
TEST CONDITIONS
I
OH
= 1mA, I
OL
= 1mA
MIN
TYP
MAX
30
UNITS
ns
w
PD Rev 3.0 November 2002
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
