WM8150
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1.
Production Data
The WM8150 processes the sampled video signal on VINP with respect to the video reset level or an
internally/externally generated reference level through the analogue processing channel.
This processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit
Programmable Gain Amplifier (PGA).
The ADC then converts each resulting analogue signal to a 12-bit digital word. The digital output from
the ADC is presented on a 4-bit wide bus.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial interface.
INPUT SAMPLING
The WM8150 has a single analogue processing channel and ADC which can be used in a flexible
manner to process both monochrome and line-by-line colour inputs.
Monochrome:
VINP is sampled, processed by the analogue channel, and converted by the ADC.
The same offset DAC and PGA register values are always applied.
Colour Line-by-Line:
VINP is sampled and processing by the analogue channel before being
converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can
be switched between the independent Red, Green and Blue digital registers (e.g. Red
→
Green→
Blue
→
Red…) at the start of each line in order to facilitate line-by-line colour operation. The
INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset
DAC. By using the INTM[1:0] bits to select the desired register values only one register write is
required at the start of each new colour line.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8150 VINP pin lies within the valid input range (0V to
VDD) the CCD output signal is usually level shifted by coupling through a capacitor, C
IN.
When
active, the RLC circuit clamps the WM8150 side of this capacitor to a suitable voltage during the
CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit.
A typical input configuration is shown in Figure 4. The Timing Control Block generates a clamp pulse,
CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8150
side of C
IN
, at VINP, is forced to the VRLC/VBIAS voltage (V
VRLC
) by switch 1. When the CL pulse
turns off, the voltage at VINP initially remains at V
VRLC
but any subsequent variation in sensor voltage
(from reset to video level) will couple through C
IN
to VINP.
RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to
the CDS/non-CDS Processing section.
w
PD Rev 3.0 November 2002
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
