Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Each of the 30 sub-addresses has a receive and a transmit
buffer, as shown in Table 7 on page 11.
Miscellaneous I/O
Several inputs are used to modify the core functionality
to simplify integration in the application. These inputs
should be tied to logic '0' or logic '1', as appropriate
(Table 6).
The memory allocated to the unused receive sub-
addresses 0 and 31 is used to provide status information
back to the rest of the system. At the end of every
transfer, a transfer status word (TSW) is written to these
locations.
Standard Memory Address Map
Core1553BRT-EBR requires an external 2,048×16 memory
device. This memory is split into 64 32-word data buffers.
Table 6 • Miscellaneous I/Os
Port Name
Type
Description
WRTCMD
In
When '1', the core will write the 1553EBR command word to the locations used for the TSW
values. If WRTTSW is also enabled, then the command word is written to memory at the start
of a message and the TSW value will overwrite the command word at the end of the
message, unless an external address mapping function is used.
WRTTSW
In
When '1', the core will write the transfer status word to the memory.
When '0', the core disables the writing of the transfer status word to memory. This is useful
for simple RT applications that do not use memory but have a direct connection to the
backend device.
EXTMDATA
INTENBBR
In
In
When '1', the core reads and writes mode code data words to and from the external memory
(except for the transmit last command and transmit BIT word). The VWORD input is not used
when this input is active.
When active '1', the core generates interrupts when both good and bad 1553EBR messages
are received. When inactive '0', the core only generates interrupts when good messages are
received.
ASYNCIF
In
In
When '1', the backend interface is in asynchronous mode.
When '0', the backend interface is in synchronous mode.
TESTTXTOUT
This input is for test use only. It should be tied low.
When high, the RT will transmit more than 32 data words if a transmit data command word
is received. This will cause the RT to shut down the transmitter and set the TIMEOUT bits in
the BIT word.
BCASTEN
In
In
This input enables broadcast operation.
When '1', broadcast operations are enabled.
When '0', broadcast messages (i.e., RT Address 31) are treated as normal messages. If the
RTADDR input is set to 31, then the RT will respond to the message.
SA30LOOP
This input alters the backend memory mapping so that sub-address 30 provides automatic
loopback (Table 7 on page 11).
When '0', the RT does not loopback sub-address 30. Separate memory buffers are used for
transmit and receive data buffers.
When '1', the RT maps the transmit memory buffer for sub-address 30 to the receive memory
buffer for sub-address 30, i.e., the upper address line is forced to '0'.
FSM_ERROR
Out
This output will go high for a single clock cycle if any of the internal state machines enter an
illegal state. This output should not go high in normal operation. Should it go high, it is
recommended that the core be reset.
10
Advanced v1.1
ACTEL [ Actel Corporation ]
