Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Table 3 •
Control and Status Signals
Port Name
CLK
CLKOUT100
CLKOUT50
RSTn
SREQUEST
RTBUSY
SSFLAG
TFLAG
VWORD[15:0]
BUSY
CMDSYNC
Type
In
Out
Out
In
In
In
In
In
In
Out
Out
Master 100 MHz clock input
100 MHz clock input routed to an output pin
50 MHz clock used to clock the protocol and memory interface blocks. All core outputs are
synchronized to this clock. Will be routed on a global network.
Asynchronous reset input (active low)
Directly controls the service request bit in the 1553EBR status word
Directly controls the busy bit in the 1553EBR status word
Directly controls the sub-system flag bit in the 1553EBR status word
Controls the sub-system flag bit in the 1553EBR status word. Can be masked by the "inhibit
terminal flag bit" mode code.
Provides the 16-bit vector value for the "transmit vector word" mode command
Indicates that the core is either receiving or transmitting data or handling a mode command
Pulses high for a single clock cycle when the RT detects the start of a 1553EBR command
word (or status word) on the bus. Provides an early signal that the RT may be about to receive
or transmit data or mode code.
Pulses high for a single cycle when the RT is about to start processing a 1553EBR message
whose command has been validated for this RT.
Pulses high for a single clock cycle when the RT receives a "synchronize" command with or
without data mode. The pulse occurs just after the 1553EBR command word (sync with no
data) or data word (sync with data mode code) has been received.
Pulses high for a single clock cycle whenever the RT receives a reset mode command. The
core logic will also automatically reset itself on receipt of this command.
Goes high when data has been received or transmitted or a mode command processed. The
reason for the interrupt is provided on INTVECT. Will stay high until INTACK goes high. If
INTACK is held high, will pulse high for a single clock cycle.
A seven-bit value containing the reason for the interrupt. Indicates which sub-address data
has been received or transmitted.
Bit 6
Bit 5
Bits 4:0
0: Bad block received
0: RX data
Sub-address
1: Good block received
1: TX data
Description
MSGSTART
SYNCNOW
Out
Out
BUSRESET
INTOUT
Out
Out
INTVECT[6:0]
Out
Further information can be found by checking the appropriate transfer status word for the
appropriate sub-address.
INTACK
MEMFAIL
In
Out
Interrupt acknowledge input. When high, resets INTOUT to low. If this input is held high, the
INTOUT signal will pulse high for one clock cycle every time an interrupt is generated.
Goes high if the core fails to read or write data to the backend interface within the required
time. This can be caused by the backend failing to assert MEMGNTn fast enough or asserting
MEMWAITn for too long.
Used to clear MEMFAIL and other internal error conditions. Must be held high for more than
two clock cycles.
CLRERR
In
Note:
All control inputs except RSTn are synchronous and sampled on the rising edge of the internally generated 50 MHz clock
(CLKOUT50). All status outputs are synchronized to the rising edge of the same clock.
A d v an c ed v1 . 1
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ACTEL [ Actel Corporation ]
