Core1553BRT-EBR Enhanced Bit Rate 1553 Remote Terminal
Table 5 •
Backend Signals
Port Name
MEMREQn
Type
Out
Description
Memory Request (active low) output. The backend interface requires memory access
completion within 1 µs of MEMREQ going low to avoid data loss or overrun on the 1553EBR
interface.*
Memory Grant (active low) input. This input should be synchronous to CLK and needs to
meet the internal register setup time. This input may be held low if the core has continuous
access to the RAM.
Memory Write (active low)
Synchronous mode: This output indicates that data is to be written on the rising clock edge.
Asynchronous mode: This output will be low for a minimum of one clock period and can be
extended by the MEMWAITn input. The address and data are valid one clock cycle before
MEMWRn is active and held for one clock cycle after MEMWRn goes inactive.
MEMRDn
Out
Memory Read (active low)
Synchronous mode: This output indicates that data will be read on the next rising clock edge.
This signal is intended as the read signal for synchronous RAMs.
Asynchronous mode: This output will be low for a minimum of one clock period and can be
extended by the MEMWAITn input. The address is valid one clock cycle before MEMRDn is
active and held for one clock cycle after MEMRDn goes inactive. The data is sampled as
MEMRDn goes high.
MEMCSn
MEMWAITn
Out
In
Memory Chip Select (active low). This output has the same timing as MEMADDR.
Memory Wait (active low)
Synchronous mode: This input is not used; it should be tied high.
Asynchronous mode: Indicates that the backend is not ready and that the core should extend
the read or write strobe period. This input should be synchronized to CLK and needs to meet
the internal register setup time. It can be permanently held high.
MEMOPER[1:0}
Out
Indicates the type of memory access being performed
00: Data transfer for both data and mode code transfers
01: TSW
10: Command word
11: Not used
MEMADDR[10:0]
MEMDOUT[15:0]
MEMDIN[15:0]
MEMCEN
Out
Out
In
Out
Address (active low). Memory address output (The sub-address mapping is covered in the
memory allocation section)
Memory Data output (active low)
Memory Data input (active low)
Control Signal Enable (active high). This signal is high when the core is requesting the
memory bus and has been granted control. It is intended to enable any tristate drivers that
may be implemented on the memory control and address lines.
Data Bus Enable (active high). This signal is high when the core is requesting the memory bus,
has been granted control, and is waiting to write data. It is intended to enable any
bidirectional drivers that may be implemented on the memory data bus.
MEMGNTn
In
MEMWRn
Out
MEMDEN
Out
Note:
*The 1 µs refers to the time from MEMREQn being asserted to the core deasserting its MEMREQn signal. The core has an internal
overhead of five clock cycles, and any inserted wait cycles will also reduce this time.
A d v an c ed v1 . 1
9
ACTEL [ Actel Corporation ]
