Advanced v1.1
Core1553BRT-EBR Enhanced Bit Rate 1553
Remote Terminal
Development System
Product Summary
•
Complete 1553BRT-EBR Implementation, Implemented
in an AX1000
Intended Use
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•
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1553 Enhanced Bit Rate Remote Terminal (RT)
Synthesis and Simulation Support
DMA Backend Interface to External Memory
Direct Backend Interface to Devices
Space and Avionic Applications
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Synthesis: Exemplar
FPGA Compiler
™
, Synplicity®, Design Compiler®,
™
•
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Key Features
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Supports Enhanced Bit Rate 1553
Verification and Compliance
10 Mbps Time-Multiplexed Serial Data Bus
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Meets Requirements of Draft SAE AS5682 Standard
(2005-10)
Interfaces to External RAM or Directly to Backend
Device
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Actel-Developed Simulation Testbench Implements
a Subset of the RT Test Plan (MIL-HDBK-1553A) for
Protocol Verification
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Synchronous or Asynchronous Backend Interface
Encoders and Decoders Operate off 100 MHz Clock
Protocol Control and Memory Interface Operates
off 50 MHz Clock
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Protocol Control Derived from Core1553BRT,
which Is Certified to MIL-STD-1553B (RT Validation
Test Plan MIL-HDBK-1553, Appendix A)
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Interfaces to Standard RS485 Transceivers
Programmable Mode Code and Sub-Address
Legality for Illegal Command Support
Contents
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Memory Address Mapping Allowing Emulation of
Legacy Remote Terminals
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Core1553BRT-EBR Device Requirements . . . . . . . . . . . . 4
Core1553BRT-EBR Verification and Compliance . . . . . . 4
Core1553BRT-EBR Fail-Safe State Machines . . . . . . . . . . 4
Enhanced Bit Rate 1553 Bus Overview . . . . . . . . . . . . . . 4
I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1553BRT-EBR Operation . . . . . . . . . . . . . . . . . . . . . . . . 14
Command Legalization Interface . . . . . . . . . . . . . . . . . 18
Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical RT Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Transceiver Loopback Delays . . . . . . . . . . . . . . . . . . . . 25
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 25
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Fail-Safe State Machines
Fully Synchronous Operation
Supported Families
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ProASIC®3/E
ProASICPLUS®
Axcelerator®
RTAX-S
Core Deliverables
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Netlist Version
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Compiled RTL Simulation Model, Compliant with
Actel Libero Integrated Design Environment (IDE)
®
Netlist Compatible with the Actel Designer
Place-and-Route Tool (with and without I/O Pads)
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RTL Version
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VHDL or Verilog Core Source Code
Synthesis Scripts
Actel-Developed Testbench (VHDL)
February 2006
Advanced v1.1
1
© 2006 Actel Corporation
ACTEL [ Actel Corporation ]
