ADuC7019/20/21/22/24/25/26/27/28/29
SECURITY
The 62 kB of Flash/EE memory available to the user can be read
and write protected.
Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 42) protects
the 62 kB from being read through JTAG programming mode.
The other 31 bits of this register protect writing to the flash
memory. Each bit protects four pages, that is, 2 kB. Write
protection is activated for all types of access.
Data Sheet
FLASH/EE CONTROL INTERFACE
Serial and JTAG programming use the Flash/EE control interface,
which includes the eight MMRs outlined in this section.
Table 31. FEESTA Register
Name
FEESTA
Address
0xFFFFF800
Default Value
0x20
Access
R
Three Levels of Protection
•
•
Protection can be set and removed by writing directly into
FEEHIDE MMR. This protection does not remain after reset.
Protection can be set by writing into the FEEPRO MMR. It
takes effect only after a save protection command (0x0C)
and a reset. The FEEPRO MMR is protected by a key to
avoid direct access. The key is saved once and must be
entered again to modify FEEPRO. A mass erase sets the
key back to 0xFFFF but also erases all the user code.
Flash can be permanently protected by using the FEEPRO
MMR and a particular value of key: 0xDEADDEAD.
Entering the key again to modify the FEEPRO register
is not allowed.
Write the bit in FEEPRO corresponding to the page to be
protected.
Enable key protection by setting Bit 6 of FEEMOD (Bit 5
must equal 0).
Write a 32-bit key in FEEADR and FEEDAT.
Run the write key command 0x0C in FEECON; wait for
the read to be successful by monitoring FEESTA.
Reset the part.
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 32.
Table 32. FEESTA MMR Bit Designations
Bit
15:6
5
4
3
Description
Reserved.
Reserved.
Reserved.
Flash interrupt status bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading the FEESTA register.
Flash/EE controller busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
Command pass. Set by the MicroConverter when a
command completes successfully. Cleared automatic-
ally when reading the FEESTA register.
Address
0xFFFFF804
Default Value
0x0000
Access
R/W
•
2
1
0
Sequence to Write the Key
1.
2.
3.
4.
5.
Table 33. FEEMOD Register
Name
FEEMOD
FEEMOD sets the operating mode of the flash control interface.
Table 34. FEEMOD MMR Bit Designations
Bit
15:9
8
7:5
4
Description
Reserved.
Reserved. This bit should always be set to 0.
Reserved. These bits should always be set to 0 except
when writing keys. See the Sequence to Write the Key
section.
Flash/EE interrupt enable. Set by user to enable the
Flash/EE interrupt. The interrupt occurs when a
command is complete. Cleared by user to disable
the Flash/EE interrupt.
Erase/write command protection. Set by user to
enable the erase and write commands. Cleared to
protect the Flash against the erase/write command.
Reserved. These bits should always be set to 0.
To remove or modify the protection, the same sequence is used
with a modified value of FEEPRO. If the key chosen is the value
0xDEAD, the memory protection cannot be removed. Only a mass
erase unprotects the part, but it also erases all user code.
The sequence to write the key is illustrated in the following
example (this protects writing Page 4 to Page 7 of the Flash):
FEEPRO=0xFFFFFFFD;
FEEMOD=0x48;
FEEADR=0x1234;
FEEDAT=0x5678;
FEECON= 0x0C;
//Protect pages 4 to 7
//Write key enable
//16 bit key value
//16 bit key value
// Write key command
The same sequence should be followed to protect the part
permanently with FEEADR = 0xDEAD and FEEDAT = 0xDEAD.
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Rev. F | Page 52 of 104
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