Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Reset Operation
Table 46. RSTSTA Register
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
Name
Address
Default Value
Access
RSTSTA
0xFFFF0230
0x01
R/W
Table 47. RSTSTA MMR Bit Designations
Bit
7:3
2
Description
Reserved.
Software reset. Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Table 44. REMAP Register
Name
Address
Default Value
0xXX1
Access
1
0
Watchdog timeout. Set automatically when a watchdog
timeout occurs. Cleared by setting the corresponding
bit in RSTCLR.
Power-on reset. Set automatically when a power-on
reset occurs. Cleared by setting the corresponding bit
in RSTCLR.
REMAP
1 Depends on the model.
0xFFFF0220
R/W
Table 45. REMAP MMR Bit Designations
Bit
Name
Description
4
Read-only bit. Indicates the size of the Flash/EE
memory available. If this bit is set, only 32 kB of
Flash/EE memory is available.
Read-only bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
Table 48. RSTCLR Register
Name
Address
Default Value
Access
RSTCLR
0xFFFF0234
0x00
W
3
Note that to clear the RSTSTA register, the user must write 0x07
to the RSTCLR register.
2:1
0
Reserved.
Remap Remap bit. Set by user to remap the SRAM to
Address 0x00000000. Cleared automatically
after reset to remap the Flash/EE memory to
Address 0x00000000.
Rev. F | Page 55 of 104
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