ATmega329/3290/649/6490
Port D also serves the functions of various special features of the
ATmega329/3290/649/6490 as listed on page 73.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega329/3290/649/6490 as listed on page 75.
Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-
tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset
occurs.
Port F also serves the functions of the JTAG interface.
Port G (PG5..PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port G pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega329/3290/649/6490 as listed on page 75.
Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port H output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port H pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the ATmega3290/6490 as
listed on page 75.
Port J (PJ6..PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port J output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port J pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port J also serves the functions of various special features of the ATmega3290/6490 as
listed on page 75.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
16 on page 41. Shorter pulses are not guaranteed to generate a reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
7
2552HS–AVR–11/06
XTAL1
ATMEL [ ATMEL CORPORATION ]
