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RS8953SPBEPJ 参数 Datasheet PDF下载

RS8953SPBEPJ图片预览
型号: RS8953SPBEPJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高比特率数字用户线( HDSL )信道单元 [High-Bit-Rate Digital Subscriber Line (HDSL) channel unit]
分类和应用: 电信集成电路
文件页数/大小: 173 页 / 1229 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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3.0 Circuit Descriptions  
RS8953B/8953SPB  
3.2 PCM Channel  
HDSL Channel Unit  
3.2 PCM Channel  
The Pulse Code Multiplexed (PCM) channel displayed in Figure 3-3 consists of  
independent transmit and receive formatter circuits to control the flow of serial  
data between PCM and HDSL channels, to establish alignment between PCM and  
HDSL frames, and maintain synchronization between PCM and HDSL clocks.  
Framed serial data consists of a variable number of multiplexed 8-bit timeslots,  
plus an optional framing bit (F-bit), a variable number of PCM frames repeated to  
form a PCM multiframe, and a variable number of multiframes concatenated to  
form a PCM 6 ms frame. T1, E1, or custom Nx64 frame formats are selected by  
programming the PCM Formatter Registers (see Table 4-4) to define the number  
of bits per frame [FRAME_LEN; addr 0xC8], frames per multiframe [MF_LEN;  
addr 0xC6], and multiframes per 6 ms frame [MF_CNT; addr 0xC7]. Unframed  
serial data is selected in the same manner; however, the number of bits per frame  
act as a single channel rather than individual timeslots and can support PCM  
frame lengths that are not integer multiples of 8-bits.  
In framed or unframed applications, PCM timebases create a 6 ms frame  
period based on the Transmit Clock (TCLK) and Receive Clock (RCLK). PCM  
timebases are programmed to equal approximately the HDSL 6 ms frame period  
defined by the HDSL Frame Length [HFRAME_LEN; addr 0xCA] in relation to  
the master HDSL channels Bit Clock (BCLKn). The resultant PCM and HDSL  
6 ms frame intervals are used to establish alignment between PCM and HDSL  
frames, to maintain synchronization between transmit clocks by performing bit  
stuffing, and to recover PCM receive clock by comparing phase offset between  
frames.  
Figure 3-3. PCM Channel Block Diagram  
TMSYNC  
MSYNC  
TSER  
CH1 Transmit (Data and Sync)  
CH2 Transmit  
Transmit Formatter  
CH3 Transmit  
INSDAT  
INSERT  
TCLK  
PCM 6 ms Sync  
Loopback  
(Data and Sync)  
RMSYNC  
RSER  
CH1 Receive (Data and Sync)  
CH2 Receive  
Receive Formatter  
DROP  
EXCLK  
RCLK  
CH3 Receive  
Recovered  
Clock  
Master  
Sync  
DPLL  
3-4  
Conexant  
N8953BDSB