RS8953B/8953SPB
3.0 Circuit Descriptions
HDSL Channel Unit
3.2 PCM Channel
3.2.1 PCM Transmit
The PCM transmit formatter shown in Figure 3-4 accepts framed or unframed
serial data on the TSER and INSDAT inputs. Both inputs are sampled on the
clock edge selected by TCLK_SEL [CMD_2; addr 0xE6] according to the format
of the PCM Multiframe Sync (MSYNC) output. The PCM transmit timebase
outputs MSYNC to mark two clock cycles before the PCM input sample point of
bit 0, frame 0. The timebase either references the system’s Transmit Multiframe
Sync (TMSYNC) input or supplies MSYNC without regard to TMSYNC, as
controlled by the PCM_FLOAT setting [CMD_2; addr 0xE6].
Figure 3-4. PCM Transmit Block Diagram
TSER
RSER
TFIFO 1
TFIFO 2
TFIFO 3
CH1 DATA
CH2 DATA
CH3 DATA
Previous
PRBS
INSDAT
TFIFO_WL 1
CH1 TSYNC
CH2 TSYNC
CH3 TSYNC
TFIFO_WL 2
TFIFO_WL 3
HP_LOOP
INSERT
MSYNC
Routing Table
TMSYNC
TFIFO_RST
PCM Transmit Timebase
PCM
6 MS
Frame
Delay
Bit
Delay
Frame
Length
MF
Length
MF
Count
RMSYNC
TCLK
PCM_FLOAT
PCM TCLK
RCLK
= Command Register Bit
TCLK_SEL
The MSYNC leads the sampling of bit 0, frame 0, on TSER and INSDAT by
two TCLK bit positions.
If PCM_FLOAT is active, the transmit timebase ignores TMSYNC and
outputs MSYNC according to the PCM formatter register values: FRAME_LEN,
MF_LEN, and MF_CNT. In this case, MSYNC acts as PCM bus master and
supplies a multiframe sync reference to the system as illustrated in Figure 3-5, but
without a specific TMSYNC relationship.
If PCM_FLOAT is inactive, MSYNC is aligned to TMSYNC (as shown in
Figures 3-5 and 3-6). The system locates the sampling point of bit 0, frame 0,
with respect to TMSYNC by programming the number of bit delays
[TFRAME_LOC; addr 0xC0] from TMSYNC’s rising edge to bit 0 of the PCM
frame. In addition, it locates the frame 0 input sample point by programming the
additional number of frame delays [TMF_LOC; addr 0xC2] needed to mark the
first frame of a PCM multiframe.
N8953BDSB
Conexant
3-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
