RS8953B/8953SPB
3.0 Circuit Descriptions
HDSL Channel Unit
3.2 PCM Channel
If the system does not apply PCM data aligned to MSYNC, then the
application is asynchronously mapped, and the placement of timeslots, frames
and multiframes is not aligned to HDSL payload bytes, blocks, or frames.
Asynchronously mapped applications require the entire PCM serial data stream
be transported; the transmitter cannot discern timeslot or frame boundaries.
Synchronous mapping allows selective timeslot routing to HDSL channels,
thus enabling transport to multiple remote sites and allowing PCM to operate at
rates which exceed available HDSL payload. However, synchronously mapped
channels are subject to changes in transmit frame alignment, resulting from
changes of the TMSYNC reference. ETSI defines synchronous and asynchronous
mapping depending on the type of E1 transport. Bellcore requires synchronous
T1 frame mapping for F-bits to align with Z-bit positions. (Refer to frame formats
and mapping arrangements illustrated in Figures 3-16 through 3-18, and
Tables 3-2 and 3-3).
3.2.1.2 Transmit
Routing Table
Timeslot and F-bit data are shifted from PCM inputs into the TFIFO according to
the programmed transmit Routing Table [ROUTE_TBL; addr 0xED]
assignments. The routing table contains an entry for each PCM timeslot and the
system selects 1, 2, 3, or none of the HDSL transmit channels as the timeslot’s
destination. The system also selects which source (TSER, INSDAT, PRBS
generator or previous timeslot) supplies data for the destination. In this manner,
the routing table allows a single timeslot to be routed to more than one HDSL
channel, and a single timeslot to supply a repeated value to destination channels.
If INSDAT supplies source data, then the INSERT output marks PCM sampling
times corresponding to that timeslot (refer to Figure 3-7 for INSERT signal
timing). Note that INSDAT is sampled through the previous buffer and is routed
in the subsequent timeslot table entry.
3.2.1.3 PRBS Generator
Incoming PCM transmit timeslots can be replaced by a test pattern on a
per-timeslot basis, or the entire framed or unframed PCM transmit channel can be
replaced by a test pattern (see PRBS_MODE in CMD_3; addr 0xE7 and
BER_SEL in CMD_6; addr 0xF3). When test pattern is enabled on a per-timeslot
basis according to the programmed transmit routing table assignments, the PRBS
generator is only clocked during enabled timeslots and may output a single test
pattern sequence over multiple discontinuous timeslots. The test pattern is
selected from one of four Pseudo-Random Bit Sequence (PRBS) patterns or a
programmable 8-bit fixed pattern [FILL_PATT; addr 0xEA]. PRBS pattern
4
15
23
selections are: 2 –1, 2 –1, 2 –1 and Quasi-Random Signal Sequence (QRSS),
20
15
where QRSS equals 2 –1 PRBS with 14-zero limit. The 2 –1 test pattern has an
inverter in the data path. RS8953B does not provide a mechanism to
automatically insert logic errors in the test pattern, although the capability to
synchronize and measure test pattern errors is provided by the BER meter.
N8953BDSB
Conexant
3-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
