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CY62128BLL-70SI 参数 Datasheet PDF下载

CY62128BLL-70SI图片预览
型号: CY62128BLL-70SI
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8静态RAM [128K x 8 Static RAM]
分类和应用:
文件页数/大小: 11 页 / 341 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62128B
MoBL
Capacitance
[6]
Parameter
C
IN
C
OUT
\
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
9
9
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R2
990
R1 1800Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
990
GND
Rise TIme:
1 V/ns
R1 1800Ω
V
CC
ALL INPUT PULSES
90%
10%
90%
10%
Fall TIme:
1 V/ns
THÉVENIN EQUIVALENT
639
1.77V
OUTPUT
Data Retention Characteristics
(Over the Operating Range for “LL” version only)
Parameter
V
DR
I
CCDR
t
CDR
t
R
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V, CE
1
V
CC
– 0.3V,
or CE
2
0.3V, V
IN
V
CC
– 0.3V or, V
IN
0.3V
0
70
Conditions
Min.
2.0
1.5
15
Typ.
Max.
Unit
V
µA
ns
ns
Data Retention Waveform
V
CC
CE
1
V
CC
, min.
t
CDR
DATA RETENTION MODE
V
DR
> 2 V
V
CC
, min.
t
R
or
CE2
Document #: 38-05300 Rev. *C
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