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CY62128BLL-70SI 参数 Datasheet PDF下载

CY62128BLL-70SI图片预览
型号: CY62128BLL-70SI
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8静态RAM [128K x 8 Static RAM]
分类和应用:
文件页数/大小: 11 页 / 341 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62128B
MoBL
Switching Characteristics
[7]
Over the Operating Range
62128B-55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[8, 9]
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[9]
CE
1
HIGH to High Z, CE
2
LOW to High Z
[8, 9]
CE
1
LOW to Power-up, CE
2
HIGH to Power-up
CE
1
HIGH to Power-down, CE
2
LOW to Power-down
Write Cycle Time
CE
1
LOW to Write End, CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z
[9]
WE LOW to High Z
[8, 9]
55
45
45
0
0
45
25
0
5
20
0
55
70
60
60
0
0
50
30
0
5
25
5
20
0
70
0
20
5
25
5
55
20
0
25
55
55
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
62128B-70
Min.
Max.
Unit
WRITE CYCLE
[10]
Switching Waveforms
Read Cycle No.1
[12, 13]
t
RC
ADDRESS
t
OHA
DATA OUT
t
AA
DATA VALID
PREVIOUS DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
11. No input may exceed V
CC
+ 0.5V.
12. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
13. WE is HIGH for read cycle.
Document #: 38-05300 Rev. *C
Page 5 of 11