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CY62128EV30LL-45ZXI 参数 Datasheet PDF下载

CY62128EV30LL-45ZXI图片预览
型号: CY62128EV30LL-45ZXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128K ×8)静态RAM [1 Mbit (128K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 872 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62128EV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground
Potential..........................................–0.3V to V
CC(max)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
.........................–0.3V to V
CC(max)
+ 0.3V
DC Input Voltage
.......................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Device
CY62128EV30LL
Range
Ind’l/Auto-A
Auto-E
Ambient
Temperature
–40°C to +85°C
V
CC
2.2V to
3.6V
–40°C to +125°C
Electrical Characteristics
(Over the Operating Range)
Parameter
V
OH
Description
Output HIGH Voltage
Test Conditions
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70V
V
OL
V
IH
Output LOW Voltage
Input HIGH Voltage
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70V
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IX
I
OZ
I
CC
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
max
= 1/t
RC
V
CC
= V
CCmax
I
OUT
= 0 mA
f = 1 MHz
CMOS levels
1.8
2.2
–0.3
–0.3
–1
–1
11
1.3
1
45 ns (Industrial/Auto-A)
Min
2.0
2.4
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
+1
16
2.0
4
1.8
2.2
–0.3
–0.3
–4
–4
11
1.3
1
Typ
Max
55 ns (Auto-E)
Min
2.0
2.4
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+4
+4
35
4.0
35
Typ
Max
Unit
V
V
V
V
V
V
V
V
μA
μA
mA
mA
μA
I
SB1
CE
1
> V
CC
−0.2V,
CE
2
< 0.2V
Automatic CE
Power down
V
IN
> V
CC
–0.2V, V
IN
< 0.2V)
Current — CMOS Inputs f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60V
Automatic CE
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V
Power down
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
Current — CMOS Inputs f = 0, V
CC
= 3.60V
I
SB2[7]
1
4
1
30
μA
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100
μs
ramp time from 0 to V
CC
(min) and 200
μs
wait time after V
CC
stabilization.
7. Only chip enables (CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document #: 38-05579 Rev. *E
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