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CY62128EV30LL-45ZXI 参数 Datasheet PDF下载

CY62128EV30LL-45ZXI图片预览
型号: CY62128EV30LL-45ZXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位( 128K ×8)静态RAM [1 Mbit (128K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 872 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62128EV30 MoBL
®
Figure 5. Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
> 1.5V
V
CC(min)
t
R
CE
Switching Characteristics
(Over the Operating Range)
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
10
45
35
35
0
0
35
25
0
18
10
55
40
40
0
0
40
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
0
45
10
18
0
55
5
18
10
20
10
45
22
5
20
45
45
10
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
45 ns (Industrial/Auto-A)
Min
Max
55 ns (Auto-E)
Min
Max
Unit
Notes
10. CE is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
13. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05579 Rev. *E
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