285V
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
32K/64Kx18 Low Voltage Deep Sync FIFOs
Features
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
—
I
CC
= 30 mA
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•
•
•
•
•
•
•
•
•
•
—
I
SB
= 4 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
64-pin 10x10 STQFP
Pin-compatible density upgrade to CY7C42X5V-ASC
families
Pin-compatible 3.3V solutions for CY7C4255/65/75/85
D
0 – 17
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
the CY7C42X5V Synchronous FIFO family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocks may be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be tied to V
CC
.
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
High
Density
Dual-Port
RAM Array
8Kx9
16Kx9
32Kx9
64Kx9
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE-ST ATE
OUTPUT REGISTER
OE
READ
CONTROL
4275V–1
Q
0 – 17
RCLK
REN
Cypress Semiconductor Corporation
Document #: 38-06012 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
CYPRESS [ CYPRESS SEMICONDUCTOR ]
