Overview
This figure shows the block diagram of the SoC.
16 KB
I-Cache
Security (SEC)1
I-MMU
G2_LE Core
System Interface Unit
(SIU)
16 KB
D-Cache
D-MMU
Bus Interface Unit
60x-to-PCI
Bridge
Memory Controller
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
4 KB
Interrupt
Instruction
Controller
RAM
16 KB
Data
RAM
Clock Counter
Serial
DMA
Virtual
IDMAs
System Functions
60x Bus
PCI Bus
32 bits, up to 66 MHz
32-bit RISC Microcontroller
and Program ROM
FCC1
FCC2
SCC1
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
USB 2.0
Time Slot Assigner
Serial interface
Serial Interface
2 TDM Ports
2 MII/RMII
Ports
1 8-bit Utopia
Port2
Non-Multiplexed
I/O
Notes:
1 MPC8272/8248 only
2 MPC8272/8271 only
Figure 1. SoC Block Diagram
1.1
Features
The major features of the SoC are as follows:
• Dual-issue integer (G2_LE) core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting frequencies of 266–400 MHz
— Separate 16 KB data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— Power Architecture®-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
3
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
