Overview
1
Overview
The following section provides a high-level overview of the MPC8555E features.
shows the
major functional units within the MPC8555E.
DDR
SDRAM
DDR SDRAM Controller
I
2
C Controller
DUART
GPIO
32b
IRQs
Local Bus Controller
Programmable
Interrupt Controller
CPM
Time-Slot Assigner
Serial
DMA
Security
Engine
256 Kbyte
L2 Cache/
SRAM
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
e500
Coherency
Module
Core Complex
Bus
64/32b PCI Controller
OCeaN
0/32b PCI Controller
DMA Controller
MPHY
UTOPIA
MIIs/RMIIs
TDMs
I/Os
FCC
FCC
SCC
SCC/USB
SCC
SMC
SMC
SPI
I
2
C
ROM
I-Memory
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
CPM
Interrupt
Controller
Serial Interfaces
10/100/1000 MAC
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Figure 1. MPC8555E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8555E feature set.
• Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
2
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
